BUT11AF datasheet, BUT11AF pdf, BUT11AF data sheet, datasheet, data sheet, pdf, Fairchild Semiconductor, NPN Silicon Transistor. BUT11AF. GENERAL DESCRIPTION. High-voltage, high-speed glass- passivated npn power transistor in a SOT envelope with electrically. BUT11AF NPN Silicon Transistor. Absolute Maximum Ratings TC=25°C unless otherwise noted. Symbol VCBO Parameter Collector-Base Voltage: BUT11AF.
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Reverse bias safe operating area.
August 8 Rev 1. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. Switching times waveforms with inductive load.
Test circuit resistive load. UNIT – – 1. Refer to mounting instructions for F-pack envelopes. Extension for repetitive pulse operation. Product specification This data sheet contains final product specifications.
BUT11AF datasheet, Pinout ,application circuits Isc Silicon NPN Power Transistor
Forward bias safe operating area. August 4 Ptot max and Ptot peak max lines. Typical base-emitter and collector-emitter saturation voltages.
Stress above one or more of the limiting values may cause permanent damage to the device. The information presented in this document does not form part of any bjt11af or contract, it is believed to be accurate and reliable and may be changed without notice.
August 2 Rev 1. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
No liability will be accepted by the publisher for any consequence of its use. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
Region of permissible DC operation. Oscilloscope display for VCEOsust. Normalised power derating and second breakdown curves. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. August 7 Rev 1. These are stress ratings buf11af and operation of the device at these or at any other conditions above but111af given in the Characteristics sections of this specification is not implied.
SOT; The seating plane is electrically isolated from all terminals.
NPN Silicon Transistor
Test circuit for VCEOsust. Typical base-emitter saturation voltage. Observe the general handling precautions for electrostatic-discharge sensitive devices ESDs to prevent damage to MOS but1af oxide. Test circuit inductive load. Exposure to limiting values for extended periods may affect device reliability. Switching times waveforms with resistive load. Application information Where application information is given, it is advisory and does not form part of the specification.
Typical DC current gain.